Topic — Power Semiconductor Modeling
Long-term research line: large-signal behavioral modeling of power devices (MOSFET / GaN HEMT), non-linear capacitance extraction, switching loss, and ZVS design.
First source: 2026-joe-nonlinear-capacitance-power-fet.
Questions of interest
- Where does the gap lie between datasheet small-signal capacitance and actual switching behavior, and how can it be quantified?
- How to back out continuous non-linear C–V curves from charge measurements (Q_G, Q_GS, Q_GD, Q_oss)?
- How to model the difference in C_ds physical mechanism between GaN HEMT and Si MOSFET (2DEG field-plate depletion)?
- How to verify (Q_oss consistency) and deploy (SPICE behavioral model, ZVS dead time) the extracted model?
Concept pages
- non-linear-capacitance-extraction — non-linear capacitance extraction methodology
- charge-conservation-qv — advantages of the charge-conserving Q-V model
- miller-plateau — Miller plateau voltage V_plat
- zvs-dead-time — ZVS dead-time design
Entity pages
- power-mosfet — power MOSFET
- gan-hemt — gallium-nitride high-electron-mobility transistor
- 2deg — two-dimensional electron gas (2DEG)
- spice — SPICE circuit simulation
Open questions / gaps
- Quantifying the error between measured DPT and this model (currently only theoretical derivation + worked example).
- Temperature effects on non-linear capacitance (datasheets mostly give 25°C).
- Dead-time optimization for other topologies (totem-pole PFC, LLC).